A conventional single ended comparator is shown in FIG. 1. If the MOS transistors Q1,Q3 and Q5 are identical and transistors Q2,Q4 and Q6 are identical, then when Vin=Vref, V1=V2=V3. Stage 1 comprises a depletion device such as the depletion field effect transistor Q1, and an enhancement device such as the enhancement field effect transistor Q2. Stage 1 has its input shorted to its output forcing its bias point to assume the value V1. Since stages 2 and 3 are identical to that of stage 1 their transfer characteristics will also be identical to that of stage 1. Voltage V2 will, therefore, assume the value of V1 as depicted in FIG. 2, and voltage V3 will assume the value of V1.
The comparator output V3 is a low level signal and must be amplified to produce a usable output switching level. Merely cascading additional stages identical to stage 3 will not suffice for the output amplifier because the inherent negative feedback of the stage 3 configuration, due to the fixed bias on the gate of the depletion load transistor Q5, results in low stage gain and a limited output swing. A non-feedback amplifier configuration such as shown in FIG. 3 provides high gain and a full output swing but suffers from the fact that it is not biased identically to the bias of the comparator stages. While proper transistor sizing could produce a non-offset transfer characteristic for a particular set of conditions and parameters, offset will occur as parameters vary in production. What is needed is a biasing scheme which reconfigures the comparator to operate in a way which is electrically identical to the output amplifier even though it is connected differently.